(1) Field of the Invention
The present invention relates to a field effect transistor using a nitride semiconductor and a method of manufacturing the field effect transistor that can be applied to, for example, a power transistor used in a power supply circuit or the like of a consumer product.
(2) Description of the Related Art
The group III nitride semiconductor represented by gallium nitride (GaN) is a wide-gap semiconductor, for which the band gaps of gallium nitride (GaN) and aluminum nitride (AlN) are wide, for example, 3.4 eV and 6.2 eV at room temperature, respectively, thus has a feature of high breakdown electric field and a higher electron saturation velocity than that of gallium arsenide (GaAs), silicon (Si) and the like. For this reason, field effect transistors (FET) as electronic devices for high-frequency or electronic devices for high-output using GaN-based material are now being actively researched and developed.
Nitride semiconductor material such as GaN can be mixed with AlN or indium nitride (InN) to form various mixed crystals, and thus can form a heterojunction similarly to the conventional arsenic-based semiconductor material such as GaAs. The heterojunction of a nitride semiconductor, for example, AlGaN/GaN heterostructure has such a characteristic that high concentrations of carriers occur at the hetero-interface due to spontaneous polarization and piezo polarization even in a state where the heterostructure is not doped with impurities. Consequently, in the case where an FET is made of nitride semiconductor material, the FET tends to be depletion type (normally-on), and tends not to be enhancement type (normally-off). However, most devices currently used in the power electronics market are normally-off, and normally-off devices are highly demanded for GaN-based nitride semiconductor devices.
A method of achieving a normally-off transistor has been reported by constructing a structure, in which the AlGaN layer in the AlGaN/GaN structure is made thinner only in its portion underlying the gate electrode, i.e., a recess structure is formed so that two-dimensional electron gas (2DEG) concentration is reduced to shift a threshold voltage to a positive value, or by growing a GaN layer having the plane orientation of the {11-20} plane on the principal surface of a sapphire substrate having the plane orientation of the {10-12} plane so that a polarized electric field is not generated in the direction perpendicular to the principal surface of the sapphire substrate. Here, the minus sign assigned to the Miller indices of the plane direction expediently indicates the inversion of the index following the minus sign.
As a promising structure for normally-off FET, Junction Field Effect Transistor (JFET) in which p-type AlGaN layer is formed in the gate electrode part has been proposed.
FIG. 10A is a sectional view of a field-effect transistor including a normally-off nitride semiconductor in the conventional art (for example, see Japanese Unexamined Patent Application Publication No. 2006-339561, hereinafter referred to as Patent Reference 1). FIG. 10A is a sectional view of a gate electrode, a source electrode, and a drain electrode in their alignment direction.
This field-effect transistor includes an AlN buffer layer 502, an undoped GaN layer 503, an undoped AlGaN layer 504, a p-type GaN layer 505, a high-concentration p-type GaN layer 506 that are sequentially formed on a sapphire substrate 501, and a gate electrode 511 is ohmic-contacted to the high-concentration p-type GaN layer 506. A source electrode 509 and a drain electrode 510 are provided on the undoped AlGaN layer 504. In order to separate the field-effect transistor from other external circuits, an isolation region 507 is provided around the peripheral portion (circumference) of the field-effect transistor.
FIG. 11A is an energy band diagram in the vertical section of the gate region of the field-effect transistor, and FIG. 11B is an energy band diagram in the vertical section between the gate region and the source region.
The hetero-interface between the undoped AlGaN layer 504 and the undoped GaN layer 503 forms a junction between two undoped layers, and a groove is formed in the conduction band as shown in FIGS. 11A and 11B due to the electric charge caused by spontaneous polarization and piezo polarization. On the other hand, as shown in FIG. 11B, the groove of the conduction band is at a level lower than the Fermi level because the p-type GaN layer 505 is not connected on the undoped AlGaN layer 504 in the active regions other than the gate region, thus two-dimensional electron gas is formed even in a state where the gate voltage is not applied. However, the energy levels of the undoped AlGaN layer 504 and the undoped GaN layer 503 are raised in the gate region as shown in FIG. 11A due to the connection of the p-type GaN layer 505 to the undoped AlGaN layer 504, thus the groove of the conduction band in the hetero-interface between the undoped AlGaN layer 504 and the undoped GaN layer 503 is at almost the same position as the Fermi level. Consequently, in the state where a bias is not applied to the gate electrode, no two-dimensional electron gas is formed in the gate region, thus the FET is in the normally-off state.
In this manner, the potential energy of the AlGaN layer is raised by connecting the p-type GaN layer to a barrier layer including AlGaN in the JFET structure. Accordingly, the concentration of the two-dimensional electron gas formed directly below the gate electrode part where the p-type AlGaN layer is formed can be reduced, thus the JFET can achieve normally-off operation. Also, a p-n junction having a built-in potential greater than that of Schottky junction for jointing a metal and a semiconductor is used in the gate electrode part, thus the rising voltage of the gate can be increased.
Here, AlGaN represents AlxGa1-xN (where 0<x<1); InGaN represents InyGa1-yN (where 0<y<1); InAlGaN represents InyAlxGa1-x-yN (where 0<x<1, 0<y<1, and 0<x+y<1). This notation also applied to the following.